Nonvolatile memory circuits such as electrically erasable programmable read only memories (EEPROM) and Flash EEPROMs have been widely used for several decades in various circuit applications including computer memory, automotive applications, and video games. Each of these nonvolatile memory circuits has at least one nonvolatile memory element such as a floating gate, silicon nitride layer, programmable resistance, or other nonvolatile memory element that maintains a data state when an operating voltage is removed. Many new applications, however, require the access time and packing density of previous generation nonvolatile memories in addition to low power consumption for battery powered circuits. One nonvolatile memory technology that is particularly attractive for these low power applications is the ferroelectric memory cell, which uses a ferroelectric capacitor for a nonvolatile memory element. A major advantage of these ferroelectric memory cells is that they require approximately three orders of magnitude less energy for write operations than previous generation floating gate memories. Furthermore, they do not require high voltage power supplies for programming and erasing charge stored on a floating gate. Thus, circuit complexity is reduced and reliability increased.
The term ferroelectric is something of a misnomer, since present ferroelectric capacitors contain no ferrous material. Typical ferroelectric capacitors include a dielectric of ferroelectric material formed between two closely-spaced conducting plates. One well-established family of ferroelectric materials known as perovskites has a general formula ABO3. This family includes Lead Zirconate Titanate (PZT) having a formula Pb(ZrxTi1-x)O3. This material is a dielectric with a desirable characteristic that a suitable electric field will displace a central atom of the lattice. This displaced central atom, either Titanium or Zirconium, remains displaced after the electric field is removed, thereby storing a net charge. Another family of ferroelectric materials is Strontium Bismuth Titanate (SBT) having a formula SbBi2Ta2O9. SBT has several advantages over PZT. Memories fabricated from either ferroelectric material have a destructive read operation. In other words, the act of reading a memory cell destroys the stored data so that it must be rewritten before the read operation is terminated.
A typical one-transistor, one-capacitor (1T1C) ferroelectric memory cell of the prior art is illustrated at FIG. 1. The ferroelectric memory cell is similar to a 1T1C dynamic random access memory (DRAM) cell except for ferroelectric capacitor 100. The ferroelectric capacitor 100 is connected between plate line 110 and storage node 112. Access transistor 102 has a current path connected between bit line 108 and storage node 112. A control gate of access transistor 102 is connected to word line 106 to control reading and writing of data to the ferroelectric memory cell. This data is stored as a polarized charge corresponding to cell voltage VCAP. Capacitance of bit line BL is represented by capacitor CBL 104.
Referring to FIG. 2, there is a hysteresis curve corresponding to the ferroelectric capacitor 100. The hysteresis curve includes net charge Q or polarization along the vertical axis and applied voltage along the horizontal axis. By convention, the polarity of the ferroelectric capacitor voltage is defined as shown in FIG. 1. A stored “0”, therefore, is characterized by a positive voltage at the plate line terminal with respect to the access transistor terminal. A stored “1” is characterized by a negative voltage at the plate line terminal with respect to the access transistor terminal. A “0” is stored in a write operation by applying a voltage Vmax across the ferroelectric capacitor. This stores a saturation charge Qs in the ferroelectric capacitor. The ferroelectric capacitor, however, includes a linear component in parallel with a switching component. When the electric field is removed, therefore, the linear component discharges and only the residual charge Qr remains in the switching component. The stored “0” is rewritten as a “1” by applying −Vmax to the ferroelectric capacitor. This charges the linear and switching components of the ferroelectric capacitor to a saturation charge of −Qs. The stored charge reverts to −Qr when the voltage across the ferroelectric capacitor is removed. Finally, coercive points VC and −VC are minimum voltages on the hysteresis curve that will degrade a stored data state. For example, application of VC across a ferroelectric capacitor will degrade a stored “1” even though it is not sufficient to store a “0”. Thus, it is particularly important to avoid voltages near these coercive points unless the ferroelectric capacitor is being accessed. Moreover, power supply voltage across a ferroelectric capacitor must exceed these coercive voltages during a standby or sleep mode avoid data loss.
Referring to FIG. 3, there is illustrated a typical write sequence for a ferroelectric memory cell as in FIG. 1. Initially, the bit line (BL), word line (WL), and plate line (PL) are all low. The upper row of hysteresis curves illustrates a write “1” and the lower row represents a write “0”. Either a “1” or “0” is initially stored in each exemplary memory cell. The write “1” is performed when the bit line BL and word line WL are high and the plate line PL is low. This places a negative voltage across the ferroelectric capacitor and charges it to −Qs. When plate line PL goes high, the voltage across the ferroelectric capacitor is 0 V, and the stored charge reverts to −Qr. At the end of the write cycle, both bit line BL and plate line PL go low and stored charge −Qr remains on the ferroelectric capacitor. Alternatively, the write “0” occurs when bit line BL remains low and plate line PL goes high. This places a positive voltage across the ferroelectric capacitor and charges it to Qs representing a stored “0”. When plate line PL goes low, the voltage across the ferroelectric capacitor is 0 V, and the stored charge reverts to Qr representing a stored “0”.
A read operation is illustrated at FIG. 4 for the ferroelectric memory cell at FIG. 1. The upper row of hysteresis curves illustrates a read “0”. The lower row of hysteresis curves illustrates a read “1”. Word line WL and plate line PL are initially low. Bit lines BL are precharged low. At time t0 bit line precharge signal PRE goes low, permitting the bit lines BL to float. At time t1 word line WL goes high and at time t2 plate line PL goes high. This permits each memory cell to share charge with a respective bit line. A stored “1” will share more charge with parasitic bit line capacitance CBL and produce a greater bit line voltage than the stored “0” as shown at time t3. A reference voltage (not shown) is produced at each complementary bit line of an accessed bit line. This reference voltage is between the “1” and “0” voltages. Sense amplifiers are activated at time t3 to amplify the difference voltage between the accessed bit line and the complementary bit line. When respective bit line voltages are fully amplified, the read “0” curve cell charge has increased from Qr to Qs. By way of comparison, the read “1” data state has changed from a stored “1” to a stored “0”. Thus, the read “0” operation is nondestructive, but the read “1” operation is destructive. At time t4, plate line PL goes low and applies −Vmax to the read “1” cell, thereby storing −Qs. At the same time, zero voltage is applied to the read “0” cell and charge Qr is restored. At the end of the read cycle, signal PRE goes high and precharges both bit lines BL to zero volts or ground. Thus, zero volts is applied to the read “1” cell and −Qr is restored.
Referring now to FIG. 5, a pulse sensing read operation is illustrated for a ferroelectric memory circuit. The read operation begins at time t0 when precharge signal PRE goes low, permitting the bit lines BL to float. Word line WL and plate line PL are initially low, and bit lines BL are precharged low. At time t1, word line WL goes high, thereby coupling a ferroelectric capacitor to a respective bit line. Then plate line PL goes high at time t2, thereby permitting each memory cell to share charge with the respective bit line. The ferroelectric memory cells share charge with their respective bit lines BL and develop respective difference voltages. Here, V1 represents a data “1” and V0 represents a data “0”. Plate line PL then goes low prior to time t3, and the common mode difference voltage goes to near zero. The difference voltage available for sensing is the difference between one of V1 and V0 at time t3 and a reference voltage (not shown) which lies approximately midway between voltages V1 and V0 at time t3. The difference voltage is amplified at time t3 by respective sense amplifiers and full bit line BL voltages are developed while the plate line PL is low. Thus, the data “1” cell is fully restored while plate line PL is low and the data “1” bit line BL is high. Subsequently, the plate line PL goes high while the data “0” bit line BL remains low. Thus, the data “0” cell is restored. The plate line PL goes low at time t4, and precharge signal PRE goes high at time t5. The high level of precharge signal PRE precharges the bit lines to ground or Vss. The word line WL goes low at time t6, thereby isolating the ferroelectric capacitor from the bit line and completing the pulse sensing cycle.
Referring to FIG. 6, there is a schematic diagram of a column of ferroelectric memory cells of the prior art. A ferroelectric memory array includes plural columns of memory cells arranged in parallel. The memory array also includes plural rows of memory cells defined by N parallel word lines WL0 through WLN−1. The memory cells are arranged in pairs and coupled to adjacent word lines and complementary bit lines BL and /BL. For example, word line WL0 is connected to a control terminal of access transistor 608. Access transistor 608 has a current path coupled between bit line /BL and ferroelectric capacitor 610. Ferroelectric capacitor 610 is coupled to a common plate line terminal PL. Word line WL1 is connected to a control terminal of access transistor 612. Access transistor 612 has a current path coupled between bit line BL and ferroelectric capacitor 614. Ferroelectric capacitor 614 is also coupled to a common plate line terminal PL. The column further includes a bit line precharge circuit having two n-channel transistors arranged to precharge bit lines BL and /BL to VSS or ground in response to a high level of precharge signal PRE.
A bit line restore circuit includes p-channel transistors 602 through 606 and is arranged to restore either bit line BL or /BL to VDD during a read or write back operation in response to a data state. N-channel transfer gate transistors couple bit lines BL and /BL to latch lines LAT and /LAT, respectively, in response to control signal TG. A bit line reference circuit is arranged to apply voltage VREF to one of bit lines BL and /BL during a read operation. For example, if a memory cell connected to bit line BL is selected, complementary bit line /BL receives reference voltage VREF. Likewise, if a memory cell connected to bit line /BL is selected, bit line BL receives reference voltage VREF. Sense amplifier 600 amplifies a difference voltage between bit lines BL and /BL during a read operation in response to control signal SAEN (not shown in FIG. 6) which enables sense amplifier 600 and applies the amplified data signal to complementary local I/O lines LIO and /LIO via n-channel read/write transistors in response to a high level of control signal R/W.
The one-transistor, one-capacitor (1T1C) memory cell of FIG. 6 offers an advantage of small layout area. One disadvantage, however, is that each word line must be raised at least an n-channel transistor threshold (Vt) above the greatest bit line voltage to transfer a full level of VDD to the memory cell. For example, if bit line (BL) voltage is 1.6 V and the threshold voltage of n-channel access transistor 612 is 0.5 V, then word line WL1 must be raised to at least 2.1 V to apply the full 1.6 V to ferroelectric capacitor 614. This requires a high voltage word line drive circuit as well as high voltage access transistors in the memory cells. High voltage transistors required for the word line drive circuit and for the access transistors increase process complexity and manufacturing cost.
Referring to FIG. 7, there is a schematic diagram showing parasitic leakage current paths of a three-transistor, one-capacitor (3T1C) ferroelectric memory of the prior art as disclosed in U.S. Pat. No. 7,804,702 (TI-62631), filed Feb. 29, 2008, and incorporated herein by reference in its entirety. The 3T1C cell or 4T1C cell disclosed therein may be used to replace the 1T1C memory cells of FIG. 6. These cells advantageously eliminate the need for high voltage transistors in the word line drive circuit and in the memory cells. The 3T1C memory cell includes n-channel access transistor 704 having a current path between bit line BL(/BL) and ferroelectric capacitor 706 and having a gate coupled to word line WL. A p-channel access transistor 700 has a parallel current path between bit line BL(/BL) and ferroelectric capacitor 706 and a gate coupled to complementary word line WLB. An n-channel shunt transistor 702 has a current path connected across ferroelectric capacitor 706 to prevent any undesired coercive voltage as previously discussed with regard to FIG. 2. The gate of n-channel transistor 702 is also connected to complementary word line WLB.
In operation, word line WL is normally low and complementary word line WLB is normally high when the memory cell of FIG. 7 is unselected. In this mode, p-channel transistor 700 and n-channel transistor 704 are off. Plate line PL is low. Shunt transistor 702, however, is on to assure long-term data retention in ferroelectric capacitor 706. When the memory cell of FIG. 7 is selected, word line WL goes high and complementary word line WLB goes low. This turns off n-channel shunt transistor 702 and connects ferroelectric capacitor 706 to bit line BL(/BL) via p-channel access transistor 700 and n-channel access transistor 704. Because of the complementary conductivity of the access transistors, it is not necessary to drive either word line WL or complementary word line WLB beyond the normal operating voltage range of 0 V to VDD. This advantageously permits the use of low voltage transistors as in peripheral circuits and avoids a need for high voltage transistors in either the memory cells or in word line drive circuits. One problem with this memory cell, however, is shown as parasitic current leakage paths A-C when the memory cell is unselected. During an active mode of operation such as a read or write operation, these parasitic leakage path currents are negligible compared to the active current. In standby or sleep modes of operation, however, they may significantly degrade the battery charge in portable electronic devices.
Path A is a parasitic leakage current path from the n-well or bulk terminal to the drain of p-channel transistor 700. The bit line BL(/BL) is normally precharged to VSS or ground and the n-well or bulk terminal is at VDD in standby and sleep modes. This leakage path may be, for example, 1.37 pA for an unselected bit line. Path B is a parasitic leakage current path from the n-well or bulk terminal to the source of p-channel transistor 700. The plate line PL is normally held at to VSS or ground and the n-well or bulk terminal is at VDD. N-channel shunt transistor 702 conducts the current of path B to plate line PL and may be, for example, 1.37 pA. Path C is a parasitic leakage current path between n-well (VDD) and p-substrate (VSS). It is typically less than paths A and B due to the linear junction and may be, for example, 0.62 pA. The total parasitic current leakage for paths A-C, therefore, may be 3.36 pA for each memory cell or 4.30 μA for a 1.28 Mbit memory array. The present invention is directed to avoiding these and other disadvantages as will be discussed in detail.